A deep dive into hardware implementation of post-quantum cryptography and why it matters, using Hamming Quasi-Cyclic (HQC), one of NIST’s newly selected post-quantum standards, as a concrete example. The lecture opens by making the case for hardware implementation of PQC, then uses HQC as a case study to walk through a typical hardware development workflow, profiling the algorithm to identify computational bottlenecks, building a state-of-the-art hardware implementation, and benchmarking it against software and hardware–software co-design alternatives. It closes with what is, to our knowledge, the only existing power side-channel attack on an HQC hardware implementation and the countermeasures it motivates. Attendees leave equipped to reason about performance, resource, and security trade-offs when designing or evaluating post-quantum cryptographic hardware.